"A Single-Electron-Transistor Logic Gate Family and Its Application - Part ..."

Hiroshi Inokawa et al. (2004)

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DOI: 10.1109/ISMVL.2004.1319953

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/ismvl/InokawaTDAH04
Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. ISMVL 2004: 269-274

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