"Systolic VLSI realization of a novel iterative division algorithm over ..."

Chien-Hsing Wu et al. (2001)

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DOI: 10.1109/ISCAS.2001.922162

access: closed

type: Conference or Workshop Paper

metadata version: 2018-08-16

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Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. ISCAS (4) 2001: 33-36

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