"A 17.28-Gb/s Transceiver With Hybrid Phase-Interpolated Clock and Data ..."

Shuo Han et al. (2026)

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DOI: 10.1109/ISCAS66217.2026.11562809

access: closed

type: Conference or Workshop Paper

metadata version: 2026-06-24

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Shuo Han, Sheng-You Liu, Kai-Hung Chou, Min-Shu Shih, Ping-Heng Wu, Ching-Yuan Yang:
A 17.28-Gb/s Transceiver With Hybrid Phase-Interpolated Clock and Data Recovery in 40-nm CMOS. ISCAS 2026: 100-104

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