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"Phase-Change Memory Based Passive Timing Circuits for DRAM Refresh Management."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Anjunyi Fan et al. (2026)

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DOI: 10.1109/ISCAS66217.2026.11562264

access: closed

type: Conference or Workshop Paper

metadata version: 2026-06-24

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  dblp key:
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  - https://dblp.org/rec/conf/iscas/FanLSLYY26
Anjunyi Fan, Yingming Lu, Guangyu Sun, Bing Li, Bonan Yan, Yuchao Yang:
Phase-Change Memory Based Passive Timing Circuits for DRAM Refresh Management. ISCAS 2026: 469-473

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