"Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and ..."

Balaji Narasimham et al. (2019)

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DOI: 10.1109/IRPS.2019.8720408

access: closed

type: Conference or Workshop Paper

metadata version: 2019-05-31

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Balaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva:
Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes. IRPS 2019: 1-4

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