"Power-Aware Mitigation of Logic Soft Error Rates at the 3-nm Bulk FinFET Node."

Jenna B. Kronenberg et al. (2025)

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DOI: 10.1109/IRPS48204.2025.10983458

access: closed

type: Conference or Workshop Paper

metadata version: 2025-06-04

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Jenna B. Kronenberg, Y. Xiong, Nicholas J. Pieper, Dennis R. Ball, Bharat L. Bhuva:
Power-Aware Mitigation of Logic Soft Error Rates at the 3-nm Bulk FinFET Node. IRPS 2025: 1-5

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