"Low power analysis of DLX processor datapath using a novel clocking scheme."

Rajesh Kannan Megalingam et al. (2010)

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DOI: 10.1145/1741906.1742107

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - https://dblp.org/rec/conf/icwet/MegalingamHRMP10
Rajesh Kannan Megalingam, Shekhil Hassan Thavalengal, Tanmay Muralidhar Rao, Ashwin Mohan, Vivek Periye:
Low power analysis of DLX processor datapath using a novel clocking scheme. ICWET 2010: 874-879

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