"A VLSI Architecture for MQ Arithmetic Encoder Supporting Three-Context ..."

Peijun Ma et al. (2024)

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DOI: 10.1109/ICVISP64524.2024.10959159

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type: Conference or Workshop Paper

metadata version: 2025-06-11

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Peijun Ma, Cong Yao, Jiangyi Shi, Gongzhi Zhao:
A VLSI Architecture for MQ Arithmetic Encoder Supporting Three-Context Parallel Processing. ICVISP 2024: 1-4

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