"A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage ..."

Guoqing Wang et al. (2023)

> Home

Details and statistics

DOI: 10.1109/ICTA60488.2023.10364305

access: closed

type: Conference or Workshop Paper

metadata version: 2024-01-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icta3/WangZSZLWL23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icta3/WangZSZLWL23
Guoqing Wang, Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Jian Liu, Nanjian Wu, Liyuan Liu:
A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process. ICTA 2023: 120-121

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.