"A 28μm2, 0.11Hz, 4.5pW gate leakage timer using ..."

Yuya Nishio, Atsuki Kobayashi, Kiichi Niitsu (2017)

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DOI: 10.1109/ICECS.2017.8292063

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type: Conference or Workshop Paper

metadata version: 2024-10-06

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Yuya Nishio, Atsuki Kobayashi, Kiichi Niitsu:
A 28μm², 0.11Hz, 4.5pW gate leakage timer using differential leakage technique in 55nm DDC CMOS for small-footprint, low-frequency and low-power timing generation. ICECS 2017: 368-371

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