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"A Parallel and Pipelined Hardware Architecture for Fractional-Pixel Motion ..."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Yuning Zeng et al. (2022)

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DOI: 10.1109/ICCE53296.2022.9730287

access: closed

type: Conference or Workshop Paper

metadata version: 2025-12-19

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  dblp key:
  - conf/iccel/ZengZXHZHY22
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  - https://dblp.org/rec/conf/iccel/ZengZXHZHY22
Yuning Zeng, Xizhong Zhu, Guoqing Xiang, Zhijian Hao, Peng Zhang, Xiaofeng Huang, Wei Yan:
A Parallel and Pipelined Hardware Architecture for Fractional-Pixel Motion Estimation in AVS3. ICCE 2022: 1-6

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last updated on 2025-12-19 16:12 CET by the dblp team

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