"HLS Implementation of a Building Cube Stencil Computation Framework for an ..."

Daiki Furukawa et al. (2024)

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DOI: 10.1109/ICCE59016.2024.10444277

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-04

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Daiki Furukawa, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano:
HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator. ICCE 2024: 1-6

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