"FPGA Implementation of XOR-MUX based Full Adder and Truncated Multiplier ..."

Pavithara P et al. (2024)

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DOI: 10.1109/ICCCNT61001.2024.10723922

access: closed

type: Conference or Workshop Paper

metadata version: 2026-04-07

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Pavithara P, Raghapriya N. R, P. M. Dinesh, S. Gowtham, D. Viji, K. Kavin Kumar, Gokul Chandrasekaran:
FPGA Implementation of XOR-MUX based Full Adder and Truncated Multiplier for Signal Processing Applications. ICCCNT 2024: 1-5

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