"Low Power Optimization of Hybrid Logic Full Adder Design using FinFET 32nm ..."

Sanjeev Kumar, Kanika Jindal, Pavan Kumar Shukla (2024)

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DOI: 10.1109/IC3I61595.2024.10828606

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type: Conference or Workshop Paper

metadata version: 2025-02-28

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Sanjeev Kumar, Kanika Jindal, Pavan Kumar Shukla:
Low Power Optimization of Hybrid Logic Full Adder Design using FinFET 32nm Technology. IC3I 2024: 345-349

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