"A New Implementation of Tapped-Delay-Line Based High-Performance ..."

Dianhang Sun, Yonggang Wang (2025)

> Home

Details and statistics

DOI: 10.1109/I2MTC62753.2025.11079001

access: closed

type: Conference or Workshop Paper

metadata version: 2025-07-31

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/i2mtc/SunW25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/i2mtc/SunW25
Dianhang Sun, Yonggang Wang:
A New Implementation of Tapped-Delay-Line Based High-Performance Time-to-Digital Converter on Xilinx Kintex-7 FPGA. I2MTC 2025: 1-5

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.