"FPGA Realization of Hardware-Flexible Parallel Structure FIR Filters Using ..."

Xuefeng Dai et al. (2020)

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DOI: 10.1109/I2MTC43012.2020.9129340

access: closed

type: Conference or Workshop Paper

metadata version: 2025-03-03

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Xuefeng Dai, Jun Gu, Peng Ye, Yu Zhao, Kuojun Yang:
FPGA Realization of Hardware-Flexible Parallel Structure FIR Filters Using Combined Systolic Arrays. I2MTC 2020: 1-5

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