"Reconfigurable Low-latency Memory System for Sparse Matricized Tensor ..."

Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna (2021)

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DOI: 10.1109/HPEC49654.2021.9622851

access: closed

type: Conference or Workshop Paper

metadata version: 2021-12-06

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Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna:
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA. HPEC 2021: 1-7

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