"On-chip memory efficient data layout for 2D FFT on 3D memory integrated FPGA."

Shreyas G. Singapura, Rajgopal Kannan, Viktor K. Prasanna (2016)

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DOI: 10.1109/HPEC.2016.7761606

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Shreyas G. Singapura, Rajgopal Kannan, Viktor K. Prasanna:
On-chip memory efficient data layout for 2D FFT on 3D memory integrated FPGA. HPEC 2016: 1-7

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