"BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism."

Suhas K. Vittal, Moinuddin Qureshi (2026)

Details and statistics

DOI: 10.1109/HPCA68181.2026.11408565

access: closed

type: Conference or Workshop Paper

metadata version: 2026-03-25