"Leakage power reduction for coarse grained dynamically reconfigurable ..."

Yoshiki Saito et al. (2008)

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DOI: 10.1109/FPT.2008.4762410

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano:
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. FPT 2008: 329-332

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