"Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage."

Junius Pun et al. (2025)

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DOI: 10.1109/FPL68686.2025.00016

access: closed

type: Conference or Workshop Paper

metadata version: 2026-03-31

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Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah:
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. FPL 2025: 27-36

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