"Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A ..."

Shankarram Athreya et al. (2018)

> Home

Details and statistics

DOI: 10.1109/ESSCIRC.2018.8494254

access: closed

type: Conference or Workshop Paper

metadata version: 2019-11-12

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/esscirc/AthreyaHKCVSZKW18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/esscirc/AthreyaHKCVSZKW18
Shankarram Athreya, Hiva Hedayati, Shayan Kazemkhani, Yanfei Chen, Saurabh Vats, Michael D. Scott, Bart Zeydel, Peter Keller, Jian Wang, Bhaskarareddy Avula, Boris Murmann, Echere Iroaga:
Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver. ESSCIRC 2018: 250-253

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.