"A 14-mW, 153.6-MHz clock-rate Δ∑ modulator for WCDMA with 77-dB ..."

Olujide A. Adeniran, Andreas Demosthenous (2007)

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DOI: 10.1109/ESSCIRC.2007.4430289

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-18

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Olujide A. Adeniran, Andreas Demosthenous:
A 14-mW, 153.6-MHz clock-rate Δ∑ modulator for WCDMA with 77-dB SFDR using constant resistance CMOS input sampling switch. ESSCIRC 2007: 244-247

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