"How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip ..."

Matthias Függer, Andreas Dielacher, Ulrich Schmid (2010)

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DOI: 10.1109/EDCC.2010.35

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/edcc/FuggerDS10
Matthias Függer, Andreas Dielacher, Ulrich Schmid:
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. EDCC 2010: 230-239

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