"Systematic Reverse Engineering of Cache Slice Selection in Intel Processors."

Gorka Irazoqui, Thomas Eisenbarth, Berk Sunar (2015)

> Home

Details and statistics

DOI: 10.1109/DSD.2015.56

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/dsd/IrazoquiES15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dsd/IrazoquiES15
Gorka Irazoqui, Thomas Eisenbarth, Berk Sunar:
Systematic Reverse Engineering of Cache Slice Selection in Intel Processors. DSD 2015: 629-636

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.