"Architectural Design of a Fast Floating-Point Multiplication-Add Fused ..."

Chichyang Chen, Liang-An Chen, Jih-Ren Cheng (2001)

> Home

Details and statistics

DOI: 10.1109/DSD.2001.952324

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/dsd/ChenCC01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dsd/ChenCC01
Chichyang Chen, Liang-An Chen, Jih-Ren Cheng:
Architectural Design of a Fast Floating-Point Multiplication-Add Fused Unit Using Signed-Digit Addition. DSD 2001: 346-353

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.