"A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment."

Gianluca Bellocchi et al. (2021)

> Home

Details and statistics

DOI: 10.1109/DSD53832.2021.00011

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/dsd/BellocchiCCM21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dsd/BellocchiCCM21
Gianluca Bellocchi, Alessandro Capotondi, Francesco Conti, Andrea Marongiu:
A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment. DSD 2021: 9-17

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.