"A Defect Tolerant and Performance Tunable Gate Architecture for ..."

Adit D. Singh (2009)

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DOI: 10.1109/DFT.2009.65

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Adit D. Singh:
A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS. DFT 2009: 422-422

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