"New Fault Models and Self-Test Generation for Microprocessors Using ..."

Artjom Jasnetski et al. (2015)

> Home

Details and statistics

DOI: 10.1109/DDECS.2015.56

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/ddecs/JasnetskiRTU15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ddecs/JasnetskiRTU15
Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar:
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. DDECS 2015: 251-254

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.