"Checking and deriving module paths in Verilog cell library descriptions."

Matthias Raffelsieper, Mohammad Reza Mousavi, Chris W. H. Strolenberg (2010)

> Home

Details and statistics

DOI: 10.1109/DATE.2010.5457050

access: closed

type: Conference or Workshop Paper

metadata version: 2020-07-11

- view
  authority control:
- export record
  dblp key:
  - conf/date/RaffelsieperMS10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/date/RaffelsieperMS10
Matthias Raffelsieper, Mohammad Reza Mousavi, Chris W. H. Strolenberg:
Checking and deriving module paths in Verilog cell library descriptions. DATE 2010: 1506-1511

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.