"BCDL: A high speed balanced DPL for FPGA with global precharge and no ..."

Maxime Nassar et al. (2010)

> Home

Details and statistics

DOI: 10.1109/DATE.2010.5456932

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

- view
  authority control:
- export record
  dblp key:
  - conf/date/NassarBDDG10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/date/NassarBDDG10
Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley:
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. DATE 2010: 849-854

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.