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"Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced ..."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Xujiang Xiang et al. (2024)

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DOI: 10.1145/3649329.3655690

access: closed

type: Conference or Workshop Paper

metadata version: 2024-11-30

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  - https://dblp.org/rec/conf/dac/XiangYLLW0Y24
Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu, Shouyi Yin:
Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. DAC 2024: 35:1-35:6

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last updated on 2024-11-30 21:10 CET by the dblp team

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