"A power-efficient FPGA accelerator: Systolic array with cache-coherent ..."

Megumi Ito, Moriyoshi Ohara (2016)

> Home

Details and statistics

DOI: 10.1109/COOLCHIPS.2016.7503681

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

- view
  authority control:
- export record
  dblp key:
  - conf/coolchips/ItoO16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/coolchips/ItoO16
Megumi Ito, Moriyoshi Ohara:
A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm. COOL Chips 2016: 1-3

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.