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"A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS."
Joseph F. Ryan, Benton H. Calhoun (2010)
- Joseph F. Ryan, Benton H. Calhoun:

A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS. CICC 2010: 1-4

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