"A 16nm 0.67pJ/bit 80Mb/s Circuit-System Co-Optimized Time Domain Brain ..."

Harshit Naman et al. (2026)

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DOI: 10.1109/CICC65509.2026.11509547

access: closed

type: Conference or Workshop Paper

metadata version: 2026-05-24

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Harshit Naman, Gourab Barik, Sarthak Antal, Samyadip Sarkar, Ming-Che Li, Shreyas Sen:
A 16nm 0.67pJ/bit 80Mb/s Circuit-System Co-Optimized Time Domain Brain Channel Receiver. CICC 2026: 1-4

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