"Low power logic circuit and SRAM cell applications with silicon on ..."

Satoshi Inaba et al. (2004)

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DOI: 10.1109/CICC.2004.1358783

access: closed

type: Conference or Workshop Paper

metadata version: 2017-08-21

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Satoshi Inaba, Hajime Nagano, Kiyotaka Miyano, Ichiro Mizushima, Yasunori Okayama, Takahiro Nakauchi, Kazunari Ishimaru, Hidemi Ishiuchi:
Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology. CICC 2004: 225-228

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