"A 10GHz Double-Edge Sampling PLL with 12.8fsrms Jitter and -257.8dB FoMJ ..."

Feng Bu et al. (2026)

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DOI: 10.1109/CICC65509.2026.11509574

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type: Conference or Workshop Paper

metadata version: 2026-06-03

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Feng Bu, Depeng Sun, Ge Wang, Zonglin Li, Zhou Shu, Bowen Wang, Hao Xu, Na Yan, Ruixue Ding, Shubin Liu, Zhangming Zhu:
A 10GHz Double-Edge Sampling PLL with 12.8fsrms Jitter and -257.8dB FoMJ in 65nm CMOS Process. CICC 2026: 1-4

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