"A 39-Gb/s PAM-3 Transmitter and ADC-Based Receiver Chipset in CMOS ..."

Yen-Po Lin et al. (2024)

> Home

Details and statistics

DOI: 10.1109/A-SSCC60305.2024.10849048

access: closed

type: Conference or Workshop Paper

metadata version: 2025-09-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/asscc/LinLLTHP24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asscc/LinLLTHP24
Yen-Po Lin, Chun-Chang Lu, Mei-Hsuan Lu, Yueh-Cheng Tsai, Ping-Hsuan Hsieh, Pen-Jui Peng:
A 39-Gb/s PAM-3 Transmitter and ADC-Based Receiver Chipset in CMOS Technologies. A-SSCC 2024: 1-3

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.