"A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency ..."

Shinichi Ikeda et al. (2023)

> Home

Details and statistics

DOI: 10.1109/A-SSCC58667.2023.10348001

access: closed

type: Conference or Workshop Paper

metadata version: 2024-01-27

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/asscc/IkedaIOSISKEMSTSA23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asscc/IkedaIOSISKEMSTSA23
Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama:
A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems. A-SSCC 2023: 1-3

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.