"A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency ..."

Martin Cochet et al. (2017)

> Home

Details and statistics

DOI: 10.1109/ASSCC.2017.8240218

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/asscc/CochetCLARA17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asscc/CochetCLARA17
Martin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran:
A 0.40pJ/cycle 981 μm² voltage scalable digital frequency generator for SoC clocking. A-SSCC 2017: 69-72

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.