"A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope ..."

Peng Chen et al. (2017)

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DOI: 10.1109/ASSCC.2017.8240224

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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Peng Chen, Feifei Zhang, Zhirui Zong, Hao Zheng, Teerachot Siriburanon, Robert Bogdan Staszewski:
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. A-SSCC 2017: 93-96

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