"A sample-and-hold circuit for 10-bit 100MS/s pipelined ADC."

Haitao Wang et al. (2011)

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DOI: 10.1109/ASICON.2011.6157226

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-25

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Haitao Wang, Hui Hong, Lingling Sun, Zhiping Yu:
A sample-and-hold circuit for 10-bit 100MS/s pipelined ADC. ASICON 2011: 480-483

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