"ADDLL/VDD-biasing co-design for process characterization, performance ..."

Jinn-Shyan Wang et al. (2011)

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DOI: 10.1109/ASICON.2011.6157119

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-25

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Jinn-Shyan Wang, Yung-Chen Chien, Jia-Hong Lin, Chun-Yuan Cheng, Ying-Ting Ma, Chung-Hsun Huang:
ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. ASICON 2011: 47-50

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