"Impact of Device Architecture and Gate Stack Processing on the ..."

Eddy Simoen et al. (2019)

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DOI: 10.1109/ASICON47005.2019.8983679

access: closed

type: Conference or Workshop Paper

metadata version: 2020-02-12

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Eddy Simoen, Alberto Vinicius Oliveira, Anabela Veloso, Adrian Vaisman Chasin, Romain Ritzenthaler, Hans Mertens, Naoto Horiguchi, Cor Claeys:
Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors. ASICON 2019: 1-4

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