"A reconfigurable linear array processor architecture for data parallel and ..."

Yucheng Liu, Jing Xie, Zhigang Mao (2011)

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DOI: 10.1109/ASICON.2011.6157322

access: closed

type: Conference or Workshop Paper

metadata version: 2020-02-08

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Yucheng Liu, Jing Xie, Zhigang Mao:
A reconfigurable linear array processor architecture for data parallel and computation intensive applications. ASICON 2011: 783-786

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