"Logic Design Considerations for 0.5-Volt CMOS."

K. Joseph Hass, Jack Venbrux, Prakash Bhatia (2001)

> Home

Details and statistics

DOI: 10.1109/ARVLSI.2001.915552

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/arvlsi/HassVB01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/arvlsi/HassVB01
K. Joseph Hass, Jack Venbrux, Prakash Bhatia:
Logic Design Considerations for 0.5-Volt CMOS. ARVLSI 2001: 75-87

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.