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"An 88.6-dB SNDR Discrete-Time Delta-Sigma Modulator Using Two-Stage ..."
Chun-Yang Chiu, Yung-Hui Chung (2025)
- Chun-Yang Chiu, Yung-Hui Chung:

An 88.6-dB SNDR Discrete-Time Delta-Sigma Modulator Using Two-Stage Floating Inverter Amplifiers in 180-nm CMOS. APCCAS 2025: 1-4

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