"Interconnect area, delay and area-delay optimization for multi-level ..."

Mai Y. Ching et al. (2010)

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DOI: 10.1109/APCCAS.2010.5775086

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-01

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Mai Y. Ching, Ang T. Boon, Chin K. Yeong, Fakhrul Zaman Rokhani:
Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus. APCCAS 2010: 1143-1146

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