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ORCIDHeng Wu 0007
Person information
- affiliation: Peking University, School of Integrated Circuits (School of IC), Beijing, China
Other persons with the same name
- Heng Wu — disambiguation page
- Heng Wu 0001
![[0000-0001-7903-5879]](https://devdomain4test.ir/img/orcid-mark.12x12.png "0000-0001-7903-5879")
— Chinese Academy of Sciences, Institute of Software, Beijing, China (and 1 more) - Heng Wu 0002 — Guangdong University of Technology, Guangdong Provincial Key Laboratory of Cyber-Physical System, School of Automation, Guangzhou, China
- Heng Wu 0003 — Aalborg University, Department of Energy Technology, Denmark (and 6 more)
- Heng Wu 0004 — Ludong University, College of Education, Institute of Network Technology, Yantai, Shandong, China (and 2 more)
- Heng Wu 0005 — Harbin Institute of Technology, State Key Laboratory of Robotics and Systems (HIT), Department of Mechatronics Engineering, China
- Heng Wu 0006 — Chinese Academy of Sciences, Changchun Institute of Optics, Fine Mechanics and Physics, China (and 1 more)
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2020 – today
- 2026
[c4]Kairong Guo, Haoran Lu, Rui Guo, Jiarui Wang, Chunyuan Zhao, Heng Wu, Runsheng Wang, Yibo Lin:
Standard Cell Layout Synthesis for Dual-Sided 3D-Stacked Transistors. ASP-DAC 2026: 966-972- 2025
- [c3]Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin:
A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis. DAC 2025: 1-7 - [c2]Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang:
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals. DATE 2025: 1-7 - [i2]Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang:
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals. CoRR abs/2501.15275 (2025) - [i1]Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin:
A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis. CoRR abs/2503.12512 (2025) - 2024
- [c1]Haoran Lu, Yandong Ge, Xun Jiang, Jiacheng Sun, Wanyue Peng, Rui Guo, Ming Li, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang:
First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects. VLSI Technology and Circuits 2024: 1-2
Coauthor Index
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