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2020 – today
- 2026
[c9]Kohei Horii, Koutaro Miyazaki, Shusuke Kawai, Hiroaki Ishihara:
A Binary-Weighted Switched-Capacitor Gate Driver IC for Overcoming Trade-Offs Between Driving Loss and Delay Time with Gate-Current Feedback Achieving 85% Driving Loss Reduction. ISSCC 2026: 1-3- [c8]Shusuke Kawai, Kohei Horii, Koutaro Miyazaki, Yuto Bushimata, Satoshi Takaya, Hiroaki Ishihara:
19.4 A Digital-Feedback Active-Gate-Driver IC for 600A 1200V SiC MOSFETs Supporting High-and Low-Side Drive with Simultaneous ${\text{dV}}_{\text{ds}}$/dt Control and ${\mathrm{V}}_{\text{ds}}$ Surge Suppression Enabled by Miller Capacitance Calibration. ISSCC 2026: 326-328 - 2020
- [c7]Satoshi Takaya, Hiroaki Ishihara, Kohei Onizuka:
18.7 A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics. ISSCC 2020: 298-300 - [c6]Hiroaki Ishihara, Kohei Onizuka:
18.8 A Fully-Generic-Process Galvanic Isolator for Gate Driver with 123mW 23% Power Transfer and Full-Triplex 21/14/0.5Mb/s Bidirectional Communication Utilizing Reference-Free Dual-Modulation FSK. ISSCC 2020: 300-302
2010 – 2019
- 2012
- [j2]Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka:
A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion. IEEE J. Solid State Circuits 47(8): 1820-1827 (2012) - 2011
- [c5]Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka:
A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller. CICC 2011: 1-4 - [c4]Hiroaki Ishihara, Toshiyuki Umeda, Katsuya Ohno, Shigeyasu Iwata, Fumi Moritsuka, Tetsuro Itakura, Manabu Ishibe, Keijiro Hijikata, Yasunori Maki:
A 130μA wake-up receiver SoC in 0.13μm CMOS for reducing standby power of an electric appliance controlled by an infrared remote controller. ISSCC 2011: 226-228 - 2010
- [j1]Hiroaki Ishihara, Masahiro Hosoya, Shoji Otaka, Osamu Watanabe:
A 10-MHz Signal Bandwidth Cartesian Loop Transmitter Capable of Off-Chip PA Linearization. IEEE J. Solid State Circuits 45(12): 2785-2793 (2010) - [c3]Hiroaki Ishihara, Masahiro Hosoya, Shoji Otaka, Osamu Watanabe:
A 10MHz signal bandwidth Cartesian-loop transmitter capable of off-chip PA linearization. ISSCC 2010: 66-67
2000 – 2009
- 2008
- [c2]Shoji Otaka, Masahiro Hosoya, Hiroaki Ishihara, Toru Hashimoto, Yuta Araki:
0.13 μm CMOS Cartesian loop transmitter IC with fast calibration and switching scheme from opened to closed loop. ESSCIRC 2008: 342-345 - 2005
- [c1]Tomoyuki Tanaka, Sungwoo Cha, Shinsaku Shimizu, Tsukasa Ida, Hiroaki Ishihara, Toshimasa Matsuoka
, Kenji Taniguchi, Akashi Sugimori, Hiroki Hihara:
A widely tunable Gm-C filter using tail current offset in two differential pairs. ISCAS (1) 2005: 812-815
Coauthor Index
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